Vhdl program on the way

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4 to 1 Multiplexer
Multiplexer is a digital system that outputs only one from the input based on the select lines. The following diagram shows the multiplexer. In short a multiplexer is called as a MUX. Please look at the truth table also.

There are 4 inputs D0, D1, D2, and D3 and two Select lines S1 and S2. Depending upon the select line input the Dataout will have either D0 or D1 or D2 or D3.




S1 S2 Dataout
0 0 D0
0 1 D1
1 0 D2
1 1 D3
The following code shows the VHDL Program for a 4 to 1 Mux and have a look at the waveform for the MUX.

library ieee;
use ieee.std_logic_1164.all;

entity MUX is
    port (s: in std_logic_vector(1 downto 0) ;
    datain: in std_logic_vector(3 downto 0);
    dataout: out std_logic
    );
end MUX;

architecture muxarch of mux is
begin
    process(s,datain)
    begin
        case s is
            when "00" => dataout <= datain(0);
            when "01" => dataout <= datain(1);
            when "10" => dataout <= datain(2);
            when others => dataout <= datain(3);  
        end case;
    end process;
end muxarch;

2.....3 to 8 Decoder
Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2n outputs. for example if there are 3 inputs the decoder asserts one of the 8 inputs to the output. the following diagram shows the 3 to 8 decoder.



here is the truth table

A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Whenever the inputs are 000 then the Q0 will be ON and so on.

VHDL Code for 3 to 8 decoder

Tool used: Active HDL Student Edition 7.2

library ieee;
use ieee.std_logic_1164.all;

entity dec3to8 is
  port (sel: in std_logic_vector (2 downto 0);
        res: out std_logic_vector (7 downto 0));
end dec3to8;
architecture archi of dec3to8 is
  begin
    res <=  "00000001" when sel = "000" else
            "00000010" when sel = "001" else
            "00000100" when sel = "010" else
            "00001000" when sel = "011" else
            "00010000" when sel = "100" else
            "00100000" when sel = "101" else
            "01000000" when sel = "110" else
            "10000000";
end archi;


3 bit binary to gray converter
entity  binary_to_gray is
port(b:in bit_vector(2downto 0);g:out_bitvector(2down to0)
end binary_to_greay;
ach.binary_to_gray_behav. of binary_to_gray is
begin
process(b)
begin
g(2)<=b(2);
g(2)<=b(2)xorb(1);
g(0)<=b(1)xorb(0);
end process;
end binary_to_gray_behavior;

full adder

entity fadder is
port( a,b,cin : in bit; s,cout : out bit);
end fadder;

architecture Behavioral of fadder is

begin
s <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);

end Behavioral;


d filp flop
ENTITY Dflipflop IS
PORT (Clock,Resetn,T:IN STD_LOGIC;
Q:BUFFER STD_LOGIC);
END Dflipflop;

ARCHITECTURE Behavior OF Dflipflop IS
BEGIN
PROCESS
BEGIN(Clock,Resetn)
IF Resetn='0' THEN
Q<='0';
ELSIF T='1' AND (Clock'EVENT AND Clock='1') THEN
Q<=NOT Q;
ELSE
Q<=Q;
END IF;
END PROCESS;
END Behavior;

t flip flop

entity tff is
port(t,clock, reset : in std_logic;
q : inout std_logic);
end entity tff;
architecture behavioral of tff is
begin
tflip : process(clock,reset) is
begin
if (reset = '1') then
q <= '0';
elsif (clock'event and clock = '1' ) then
q <= t xor q;
end process tflip;
end architecture behavioral;